EVAL-AD5533EB【PDF 12/16 页】32-Channel Precision Infinite Sample-and

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REV. A

–12–

AD5533B

Reset Function

The reset function on the AD5533B can be used to reset all

nodes on this device to their power-on-reset condition. This is

implemented by applying a low-going pulse of between 90ns and

200 ns to the

TRACK

RESET

pin on the device. If the applied

pulse is less than 90 ns, it is assumed to be a glitch and no opera-

tion takes place. If the applied pulse is wider than 200ns, this pin

adopts its track function on the selected channel, V

is switched to

the output buffer, and an acquisition on the channel will not occur

until a rising edge of

TRACK

Function

Normally in ISHA mode of operation,

TRACK

is held high and

the channel begins to acquire when it is addressed. However, if

TRACK

is low when the channel is addressed, V

is switched

to the output buffer and an acquisition on the channel will not

occur until a rising edge of

TRACK

. At this stage the

BUSY

will go low until the acquisition is complete, at which point the

DAC assumes control of the voltage to the output buffer and

is free to change again without affecting this output value.

This is useful in an application where the user wants to ramp up

until V

OUT

reaches a particular level (Figure 7). V

does

not need to be acquired continuously while it is ramping up.

TRACK

can be kept low and only when V

OUT

has reached its

desired voltage is

TRACK

brought high. At this stage, the

acquisition of V

begins.

In the example shown, a desired voltage is required on the output

of the pin driver. This voltage is represented by one input to a

comparator. The microcontroller/microprocessor ramps up the

input voltage on V

through a DAC.

TRACK

is kept low while

the voltage on V

ramps up so that V

is not continually

acquired. When the desired voltage is reached on the output of the

pin driver, the comparator output switches. The

P then

knows what code is required to be input in order to obtain the

desired voltage at the DUT. The

TRACK

input is now brought

high and the part begins to acquire V

BUSY

goes low until V

has been acquired. When

BUSY

goes high, the output buffer

is switched from V

to the output of the DAC.

MODES OF OPERATION

The AD5533B can be used in three different modes. These modes

are set by two mode bits, the first two bits in the serial word.

The 01 option (DAC Mode) is not available for the AD5533B.

For information on this mode, refer to the AD5532B data sheet.

If you attempt to set up DAC Mode, the AD5533B will enter a

test mode and a 24-clock write will be necessary to clear this.

Table II. Modes of Operation

Mode Bit 1

Mode Bit 2

Operating Mode

ISHA Mode

DAC Mode (Not Available)

Acquire and Readback

Readback

1. ISHA Mode

In this standard mode, a channel is addressed and that channel

acquires the voltage on V

. This mode requires a 10-bit

write (see Figure 3) to address the relevant channel

OUT

0–V

OUT

31, offset channel, or all channels). MSB is

written first.

2. Acquire and Readback Mode

This mode allows the user to acquire V

and read back the

data in a particular DAC register. The relevant channel is

addressed (10-bit write, MSB first) and V

is acquired in 16

(max). Following the acquisition, after the next falling edge

SYNC

, the data in the relevant DAC register is clocked out

onto the D

OUT

line in a 14-bit serial format (see Figure 4).

During readback, D

is ignored. The full acquisition time

must elapse before the DAC register data can be clocked out.

3. Readback Mode

Again, this is a readback mode but no acquisition is performed.

The relevant channel is addressed (10-bit write, MSB first) and

on the next falling edge of

SYNC

, the data in the relevant DAC

OUT

line in a

14-bit serial format

(see Figure 4). The user must allow 400 ns

(min) between the

last SCLK falling edge in the 10-bit write and the falling edge

SYNC

in the 14-bit readback. The serial write and read words

can be seen in Figure 8.

This feature allows the user to read back the DAC register

code of any of the channels. Readback is useful if the system

has been calibrated and the user wants to know what code in

the DAC corresponds to a desired voltage on V

OUT

INTERFACES

Serial Interface

The SER/

PAR

pin is tied high to enable the serial interface and

to disable the parallel interface. The serial interface is controlled

by four pins as follows:

SYNC

, D

, SCLK

Standard 3-wire interface pins. The

SYNC

pin is shared

with the

function of the parallel interface.

OUT

Data out pin for reading back the contents of the DAC registers.

The data is clocked out on the rising edge of SCLK and is

valid on the falling edge of SCLK.

Mode Bits

There are four different modes of operation as described above.

Cal Bit

When this is high, all 32 channels acquire V

simultaneously. The

acquisition time is then 45

s (typ) and accuracy may be reduced.

This bit is set low for normal operation.

Offset_Sel Bit

If this bit is set high, the offset channel is selected and bits

A4–A0 are ignored.

Test Bit

This must be set low for correct operation of the part.

A4–A0 Bit

Used to address any one of the 32 channels (A4 = MSB of

address, A0 = LSB).

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